This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-297698, filed Sep. 28, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a high voltage semiconductor device, and more particularly, to a power device such as an IGBT.
A conventional high voltage vertical power device will be explained below while taking the case of a punch through type IGBT using an epitaxial substrate.
FIG. 1 is a sectional view of a cell area of the conventional punch through type IGBT using the epitaxial substrate.
The epitaxial substrate comprises a positive semiconductor substrate (positive collector layer) 11 and a negative epitaxial layer formed on the semiconductor substrate 11 by an epitaxial growth method. In this example, the epitaxial layer comprises a negative buffer layer 12 and a N type drift layer (active layer) 13. For example, concentration of positive impurity in the semiconductor substrate 11 is set to about 7.5xc3x971018 atoms/cm3, concentration in the negative impurity in the buffer layer 12 is set to about 2.7xc3x971017 atoms/cm3, and concentration of negative impurity in the drift layer 13 is set to about 1.35xc3x971014 atoms/cm3.
A positive base layer 14 is formed on a surface region of the drift layer 13. A negative emitter layer 15 and a positive base contact layer 16 are formed in the positive base layer 14. A negative low resistant layer 17 which is adjacent to the positive base layer 14 is formed in the drift layer 13.
For example, surface concentration of positive impurity in the positive base layer 14 is set to about 4.0xc3x971017 atoms/cm3, surface concentration of negative impurity in the negative emitter layer 15 is set to about 1.27xc3x971020 atoms/cm3, surface concentration of positive impurity in the positive base contact layer 16 is set to about 2.8xc3x971019 atoms/cm3, and surface concentration of negative impurity in the negative low resistant layer 17 is set to about 5.0xc3x971015 atoms/cm3.
An emitter electrode 18 is formed on the negative emitter layer 15 and the positive base contact layer 16. The emitter electrode 18 is in contact with the negative emitter layer 15 and the positive base contact layer 16. A gate electrode 20 is formed on the positive base layer 14 through an insulating film 19. A collector electrode 21 is formed on a back surface of the semiconductor substrate 11.
In the conventional power device including the above-described IGBT, an epitaxial substrate is employed. However, manufacturing cost of the epitaxial substrate is high and as a result, a cost of the vertical power device is increased.
In the power device, a so-called life time control is conducted in order to enhance the turn off characteristics. As the life time is shorter, a high speed turn off is possible. Therefore, the life time has been set from a range of 5 to 10 xcexcs to about 100 ns.
However, as is well known, the turn off characteristics and the on characteristics are in a relation of trade-off. That is, if the turn off characteristics is enhanced, ON voltage becomes higher and on characteristics are deteriorated.
This trade-off relation is generated not only in the above-described punch through type device having the buffer layer, but also in a non-punch through type device having no buffer layer and in a trench gate type device.
Semiconductor devices according to first and second aspects of inventions comprise: a first conductive type first base layer; a second conductive type collector layer on a side of a first surface of the first base layer; a first conductive type buffer layer between the first base layer and the collector layer; a second conductive type second base layer on a side of a second surface of the first base layer; a first conductive type emitter layer in the second base layer; and a gate electrode above the second base layer between the emitter layer and the first base layer.
In the semiconductor device of the first aspect of the invention, the first base layer may comprise a semiconductor substrate, each of the collector layer, the second base layer and the emitter layer comprises a diffusion layer in the semiconductor substrate, and a depth of diffusion of the collector layer is 1 xcexcm or less.
In the semiconductor device of the second aspect of the invention, the following condition may be satisfied: 5xe2x89xa7bDPxc2x7QP/bDNxc2x7QN (QN is a dose amount of the buffer layer, bDN is an average of a diffusion coefficient in the buffer layer, QP is a dose amount of the collector layer, and bDP is an average of a diffusion coefficient in the collector layer).
A manufacturing method of a third aspect of a invention is applied to a semiconductor device in which a power device and its control section are formed in one chip, and comprises a step for implanting impurities into a forming region of the power device and a forming region of the control section at the same time, thereby forming a first impurity layer which becomes a portion of the power device in the forming region of the power device, and a step for forming a second impurity layer which becomes a portion of the control element in the forming region of the control section.
A manufacturing method of a fourth aspect of a invention is applied to a semiconductor device in which a power device and its control section is formed in one chip, and comprises: a step for forming a conductive film in each of a forming region of a power device and a forming region of a control section, a step for etching the conductive films by RIB using one mask, a step for forming a first electrode which becomes a portion of the power device in the forming region of the power device, and a step for forming a second electrode which becomes a portion of the control element in the forming region of the control section.